Publications

A complete list is also available on Google Scholar. My name (W. Fu) appears in bold.

Journal Articles

• FusionESP: Improved Enzyme-Substrate Pair Prediction by Fusing Protein and Chemical Knowledge.
  Z. Du, W. Fu, X. Guo, D. Caragea, Y. Li
  Journal of Chemical Information and Modeling, 65(6):2806–2817, 2025  [link]

• A Generalized Hardware Debugging Approach for Large Language Models via Semi-Synthetic Datasets.
  W. Fu, S. Li, Y. Zhao, K. Yang, X. Zhang, Y. Jin, X. Guo
  IEEE Transactions on Circuits and Systems I, 72(2):623–636, 2025  [link]

Conference Papers

• FinHardBench: Can LLMs Generate Latency-Aware Hardware for Financial Computing?.
  W. Fu, H. Zhang, M. Shao, Z. Wang, J. Knechtel, O. Sinanoglu, M. Shafique, R. Karri, X. Guo
  COLM 2026  [link]

• Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation.
  M. Shao, Z. Wang, W. Fu, X. Guo, J. Knechtel, O. Sinanoglu, R. Karri, M. Shafique
  IEEE LAD 2026 (Long)  [link]

• ScanFree: LLM-Guided Sequential ATPG for Circuits Where Scan Chains Are Inadmissible.
  W. Fu, Z. Lu, G. Qu, X. Guo
  AsianHOST 2026 (Oral)

• Control-Flow Collapse: Hijacking Mixture-of-Experts Routing via Single-Bit Faults in the Gating Path.
  W. Fu, Z. Lu, G. Qu, X. Guo
  AsianHOST 2026 (Oral)

• Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes.
  W. Fu, Z. Wang, M. Shao, R. Karri, M. Shafique, J. Knechtel, O. Sinanoglu, X. Guo
  GLSVLSI 2026  [link]

• Control-Flow Collapse: Exploiting Gating Logic in MoE Accelerators via Instruction-Level Fault Injection.
  W. Fu, Z. Lu, G. Qu, X. Guo
  GLSVLSI 2026  [link]

• Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision.
  W. Fu, S. Li, K. Yang, X. S. Zhang, Y. Jin, X. Guo
  ICCAD 2025  [link]

• EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits.
  J. Gao, W. Fu, X. Guo, W. Cao, X. Zhang
  DAC 2025  [link]

• Hardware Generation with High Flexibility Using Reinforcement Learning Enhanced LLMs.
  Y. Zhao, W. Fu, S. Li, Y.-X. Hu, X. Guo, Y. Jin
  DAC 2025  [link]

• HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation.
  W. Fu, Y. Wang, Z. Lu, X. Guo, G. Qu
  MLCAD 2025  [link]

• Rethinking LLM Safety on Edge Devices: Unearthing Hidden Vulnerabilities through Power Stress.
  W. Fu, Z. Lu, G. Qu, X. Guo
  AsianHOST 2025  [link]

• Fixbench-RTL: A Comprehensive Benchmark for Evaluating LLMs on RTL Debugging.
  S. Li, W. Fu, Y. Zhao, X. Guo, Y. Jin
  AsianHOST 2025  [link]

• Leveraging Large Language Models for Secure Hardware Verification and Analysis.
  Y. Zhao, W. Fu, Y.-X. Hu, S. Li, X. Guo, Y. Jin
  AsianHOST 2025 (Poster)  [link]

• HWFixBench: Benchmarking Tools for Hardware Understanding and Fault Repair.
  W. Fu, S. Li, Y. Jin, X. Guo
  GLSVLSI 2025  [link]

• Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM.
  S. Li, W. Fu, Y. Zhao, X. Guo, Y. Jin
  GLSVLSI 2025  [link]

• Enhancing LLM Performance on Hardware Design Generation Task via Reinforcement Learning.
  Y. Zhao, W. Fu, S. Li, Y.-X. Hu, X. Guo, Y. Jin
  ISCAS 2025  [link]

• Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain-Specific Knowledge.
  W. Fu, S. Li, Y. Zhao, H. Ma, R. G. Dutta, X. Zhang, K. Yang, Y. Jin, X. Guo
  ASP-DAC 2024  [link]

• LLM4SecHW: Leveraging Domain-Specific Large Language Model for Hardware Debugging.
  W. Fu, K. Yang, R. G. Dutta, X. Guo, G. Qu
  AsianHOST 2023  [link]

• Inter-IP Malicious Modification Detection through Static Information Flow Tracking.
  Z. Liu, O. Arias, W. Fu, Y. Jin, X. Guo
  DATE 2022  [link]

• Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms.
  W. Fu, H. Yu, O. Arias, K. Yang, Y. Jin, T. Yavuz, X. Guo
  GLSVLSI 2022  [link]

• Fuzzing Hardware: Faith or Reality?.
  W. Fu, O. Arias, Y. Jin, X. Guo
  NANOARCH 2021 (Invited)  [link]

Under Review

Several manuscripts are currently under review at peer-reviewed conferences. Titles and venues are available upon request.

Preprints

• HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking.
  Z. Wang, M. Shao, W. Fu, P. Basu Roy, X. Guo, R. Karri, M. Shafique, J. Knechtel, O. Sinanoglu
  arXiv:2604.17093, 2026

• From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design.
  W. Fu, Z. Wang, M. Shao, J. Knechtel, O. Sinanoglu, R. Karri, M. Shafique, X. Guo
  arXiv:2604.17097, 2026

• AnalogSAGE: Self-evolving Analog Design Multi-Agents with Stratified Memory and Grounded Experience.
  Z. Wang, J. Gao, W. Fu, X. Guo, X. Zhang
  arXiv:2512.22435, 2025

• VGF: Value-Guided Fuzzing — Fuzzing Hardware as Hardware.
  R. Dai, M. Lee, P. Hoey, W. Fu, T. Yavuz, X. Guo, et al.
  arXiv:2312.06580, 2023