Research

My research addresses how to make hardware design and AI systems more trustworthy, automated, and secure. I work along three intertwined directions.

1. LLMs for Hardware Design and Debugging

Modern hardware design is bottlenecked by manual RTL coding, debugging, and verification. I build domain-adapted large language models and the data infrastructure they need.

  • Hardware Phi-1.5B (ASP-DAC’24) — one of the first large language models pre-trained to encode hardware-domain knowledge.
  • LLM4SecHW (AsianHOST’23) — leveraging domain-specific LLMs for hardware debugging.
  • HADA (MLCAD’25) — multi-source training for hardware security assertion generation.
  • Reasoning LLMs for HDL (ICCAD’25) — function-aligned differentiated revision for hardware design generation.
  • HWFixBench / FixBench-RTL (GLSVLSI’25, AsianHOST’25) — public benchmarks for evaluating LLMs on RTL repair.
  • FinHardBench (COLM’26) — can LLMs generate not just correct but fast hardware? 33 financial FPGA tasks evaluated through a full synthesis and place-and-route flow, plus system-level design space exploration. [code]

2. Hardware Security and Trustworthy AI

I study how hardware-level attacks compromise AI systems deployed at the edge — and how to defend against them.

  • Control-Flow Collapse (GLSVLSI’26, AsianHOST’26) — a router holding under 0.01% of model parameters drives 100% of expert dispatch, so one bit flip in the gating path hijacks routing and collapses accuracy. Two papers: the first pairs the attack with triple modular redundancy and a validity-checker fallback, the second adds targeted expert steering under a quantifiable bit budget across two MoE architectures, and delimits what TMR cannot tolerate.
  • ScanFree (AsianHOST’26) — LLM-guided sequential ATPG for cores that ship with scan chains absent or disabled, because scan is a documented key-extraction channel.
  • Power-stress attacks on edge LLMs (AsianHOST’25) — exposing hidden failure modes via undervolting.
  • Hardware Trojan detection (GLSVLSI’22) — graph neural networks operating on intermediate representations of SoCs.
  • Hardware fuzzing (NANOARCH’21, DATE’22) — examining whether software-style fuzzing can transfer to RTL.

3. EDA Beyond Digital: Analog Circuits & Cross-Domain AI

  • EVA (DAC’25) — generative engine for novel analog circuit discovery.
  • AnalogSAGE (arXiv, 2025) — self-evolving multi-agent analog design with stratified memory and grounded experience.
  • FusionESP (JCIM’25) — applying multimodal protein/chemistry knowledge to enzyme-substrate prediction, a step toward AI security in bioinformatics.

Funding & Collaborations

My research has been supported through NSF (FMitF, PPoSS, CAREER, CICI, S&CC-PG) and Kansas NSF EPSCoR projects. I collaborate closely with groups at NYU Tandon and NYU Abu Dhabi (Prof. Ramesh Karri, Prof. Muhammad Shafique, Prof. Ozgur Sinanoglu, Dr. Johann Knechtel), the University of Maryland (Prof. Gang Qu), the University of Connecticut, and Florida (Prof. Yier Jin).